Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS Block Encoder Scrambler Alignment Marker Insertion Block Distributor TX PCS Interface TX PCS-PMA Interface 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

4.3.6. TX PCS

Figure 8. TX PCS

The TX PCS has four main components:

Block Encoder

The block encoder takes the 64-bit data blocks and 8-bit control blocks and encodes them into 66 bit encoded blocks. The TX PCS encodes two blocks per clock cycle.

Scrambler

The TX PCS scrambler takes two encoded blocks per clock cycles and scrambles them and produces two scrambled data blocks per clock cycle.

Alignment Marker Insertion

The alignment marker insertion blocks are used to insert an alignment marker on each virtual lane every 16,384 data blocks. The generation of the alignment markers.

Block Distributor

The block distributor takes the scrambled data blocks and alignment marker and distributes them round robin to the four virtual lanes.

TX PCS Interface

A description of the TX PCS interface signals is given in the table below. All signals are synchronous to the clk.
Table 11.  TX PCS Interface
Name I/O Width Description
Clk Input 1 Main register clock. Runs at 312.5 MHz.
din_d Input 128 MII data input. Takes two data blocks per cycle.
din_c Input 16 MII control input. Takes two control blocks per cycle.
din_am Input 1 Alignment marker insertion indicator. When asserted, the TX PCS ignores the data presented on the MII port and insert alignment markers instead. This should be asserted for two cycles in a row to insert all four alignment markers.
dout Output 264 Scrambled data and alignment marker output. This interface presents all four physical lane data blocks at once.
Valid Output 1 Indicates that the data presented on dout is valid. This is likely asserted every other PCS clk cycle and used to drive the PMA FIFO write signal.

TX PCS-PMA Interface

In the Low Latency 40G Ethernet design, the interface between the PCS and the TX PMA is through PMA direct PHY IP and 66 bits per virtual lane giving a total parallel width of 264 bits.

In this design the GTS PMA input data width is 80 bits. The 66 bits from PCS is converted into the respective 80-bit and forwarded to the GTS PMA as TX parallel data.

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