Visible to Intel only — GUID: izp1704169556257
Ixiasoft
Visible to Intel only — GUID: izp1704169556257
Ixiasoft
6.3. GTS Transceivers Signals
The GTS Transceiver PHY IP uses four GTS PMA transceivers for the Low Latency 40G Ethernet Intel® FPGA IP. For more information, refer to the GTS Transceiver PHY User Guide .
The transceivers require a PLL ref clk as an input. The GTS PMA transceiver is configured for a specific setting in order for the successful integration of the existing Low Latency 40G Ethernet MAC and PCS with the GTS PMA transceiver.
Clock Mode – Non-External clock mode.
tx_clkout [0] of the GTS PMA transceiver is connected to tx_coreclkin [0],[1],[2],[3].
rx_clkout [0] of the GTS PMA transceiver is connected to rx_coreclkin [0],[1],[2],[3].
Pll_reference of GTS PMA transceiver is configured to be 156.25. This also works with 312.5 MHz, however the GTS PMA transceiver must be configured again for the same.
The tx_clkout and rx_clkout is configured to be half-rate, which is 161.13 MHz.
There are two PLLs that convert the 161.13 MHz to 312.5 MHz.
The TX PLL reference clock input is tx_clkout[0], whereas the RX PLL reference clock input is rx_clkout[0].
For SYNC-E, the recovered clock that is rx_clkout[1] from GTS PMA transceiver is used. This is of frequency 312.5 MHz.
Signal |
Direction |
Width |
Description |
---|---|---|---|
tx_serial | Output | 4 | TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair. |
rx_serial | Input | 4 | RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair. |
clk_ref_p | Input | 1 | The PLL reference clock used by TX and RX. Input to the clock data recovery (CDR) circuitry in the RX PMA. |