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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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7.3. RX MAC Registers
Addr | Name | Description | Reset | Access |
---|---|---|---|---|
0x0 | RXMAC_REVID | RX MAC revision ID. | 0x0627 2016 | RO |
0x1 | RXMAC_SCRATCH | Scratch register available for testing. | 0x0000 0000 | RW |
0x2 | RXMAC_NAME_0 | First 4 characters of IP variation identifier string, "40gMACRxCSR". | 0x3430 674D | RO |
0x3 | RXMAC_NAME_1 | Next 4 characters of IP variation identifier string, "40gMACRxCSR". | 0x4143 5278 | RO |
0x4 | RXMAC_NAME_2 | Final 4 characters of IP variation identifier string, "40gMACRxCSR". | 0x004 35352 | RO |
0x6 | RXMAC_SIZE_CONFIG | Specifies the maximum frame length available. The MAC asserts l<n>_rx_error[3] when the length of the received frame exceeds the value of this register. The supported value is 64 or larger. | 0xXXXX 2580 3 | RW |
0x7 | MAC_CRC_CONFIG | The RX CRC forwarding configuration register. The following encodings are defined:
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 | RW |
0x8 | LINK_FAULT | Link Fault Status Register.
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xx00 | RO |
0x50A | RX_MAC_CONTROL | RX MAC Control Register. The following bits are defined:
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxx1 1x0x | RW |
3 X means "Don't Care".