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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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4.6.1. Frame Type Checking
The MAC TX/RX checks the length/type field to determine the frame type:
- Length/type ≤ 0x5DC(1500): The field represents the payload length of a basic Ethernet frame. The MAC TX/RX continues to check the frame and payload lengths.
- 0x5DC(1500) < Length/type < 0x600(1536): The frames with payloads size in this range are not a standard basic Ethernet frame, nor they are legal control packets. The payload length is not checked for this kind of packets.
- Length/type ≥ 0x600 (1536): The field represents the frame type instead of frame payload length
- Length/type = 0x8100. VLAN or stacked VLAN tagged frames. The MAC TX/RX continues to check the frame and payload lengths.
- Length/type = 0x8808. Control frames. The next two bytes are the Opcode field which indicates the type of control frame. For pause frames (Opcode = 0x0001) and PFC frames (Opcode = 0x0101), the MAC RX proceeds with pause frame processing.
- For other field values, the MAC RX forwards the receive frame to the client. If the length/type is less than payload, the MAC RX considers the frame to have excessive padding and does not assert rx_error[4].