Visible to Intel only — GUID: efz1704176756650
Ixiasoft
Visible to Intel only — GUID: efz1704176756650
Ixiasoft
7. Control, Status, and Statistics Register Descriptions
This section provides information about the memory-mapped registers. You access these registers using the IP's Avalon® memory-mapped control and status interface. The registers use 32-bit addresses; they are not byte addressable.
Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP variation, or to register bits that are not defined in your IP variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write meaning to values in undefined register bits.
Word Offset | Register Type |
---|---|
0x300-0x3FF | PHY registers |
0x400-0x4FF | TX MAC registers |
0x500-0x5FF | RX MAC registers |
0x800-0x8FF | Statistics Counter registers - TX direction |
0x900-0x9FF | Statistics Counter registers - RX direction |
0x1000-0x1016 | Packet Client registers |