Visible to Intel only — GUID: fiv1704169224150
Ixiasoft
Visible to Intel only — GUID: fiv1704169224150
Ixiasoft
6.1. TX MAC Interface to User Logic
Signal |
Direction |
Width |
Description |
---|---|---|---|
clk_txmac | Output | 1 | The TX clock for the IP is clk_txmac. The frequency of this clock is 312.5 MHz. This is derived from the tx_clkout[0] of the PMA. |
l2_tx_data | Input | 128 | Data input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. |
l2_tx_preamble | Input | 64 | User preamble data. Available when you turn on Enable preamble passthrough mode. User logic drives the custom preamble data when l2_tx_startofpacket is asserted.The l2_tx_preamble [63:56] has to be 8’hfb. |
l2_tx_valid | Input | 1 | When asserted, indicates valid data. |
l2_tx_startofpacket | Input | 1 | When asserted, indicates the first byte of a frame. |
l2_tx_endofpacket | Input | 1 | When asserted, indicates the end of a packet. |
l2_tx_empty | Input | 4 | Specifies the number of empty bytes when l2_tx_endofpacket is asserted. |
l2_tx_ready | Output | 1 | When asserted, indicates that the MAC can accept the data. The data is processed only when l2_tx_ready is asserted. |
l2_tx_error | Input | 1 | A high on this signal aligned with a valid EOP indicates that the current packet needs to be treated as error packet |
l2_txstatus_valid | Output | 1 | When asserted, indicates that l2_txstatus_data is driving valid data. |
l2_txstatus_data | Output | 40 | Specifies information about the transmit frame. |
l2_txstatus_error | Output | 7 | Specifies the error type in the transmit frame. |