Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description RX PMA-PCS Interface 40G PCS Compliance
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

4.4.4. RX PCS Functional Description

The RX PCS interfaces with Hard PCS/PMA block is configured in 66:40 10G PCS Basic Generic Mode, with bit slip enabled and single data-rate. Each input stream thus carries an individual virtual lane for the 40G PCS. The PCS operates at 312.5 MHz. A read control/enable logic controls the incoming data throughput by reading the hard-PCS FIFOs only half of the cycles (66*4*312.5/2 = 41.250 Gbps).

The soft RX-PCS logically consists of five stages:
  • Word Lock: The word lock is achieved for each virtual lane/word-stream by utilizing the hard-PCS bit-slipping functionality (in the PCS gearbox). This is done through a soft control logic that sends the bit-slipping command and monitors incoming stream to declare when a corresponding lane is word-locked.
  • Merge: The four incoming streams/virtual-lanes from the hard-PCS are each 66-bit wide, that are read-in with a cadence that alternates inputting data from even/odd FIFOs at every clock cycle. The four input channels thus have twice the capability to required bandwidth. This redundant capability is not available at later stages that are two 66-bit words wide. The merge stage therefore translates those four input channels into two words by merging two physical/virtual lanes on to one.
  • Lane Reordering, De-skew and Lane Alignment: The locked virtual lanes are next de-skewed in RX PCS and lanes are aligned together. This stage declares lane alignment lock status.
  • Descrambler: The aligned lanes are descrambled in this stage.
  • MII Decoding: MII data is decoded and two 64-bit words along with control signals are provided to the RX MAC.

RX PMA-PCS Interface

In the Low Latency 40G Ethernet Intel® FPGA IP design for Agilex™ 5 devices, the interface between the PCS and the RX PMA uses 66 bits per virtual lane giving a total parallel width of 264 bits. In the current design, the GTS transceiver configured is PMA direct with Gearbox 64/66. In this design the GTS PMA parallel data width is 80 bits. The 66-bit is extracted from the 80 bits GTS RX parallel data and passed onto the PCS module.

40G PCS Compliance

In Low Latency 40G Ethernet PCS design, to save resources, some logic is simplified so that it did not fully comply to IEEE802.3.

In PCS RX alignment marker lock state, the design did not use all 24 bits of alignment marker to detect AM, but only used 6 bits to do detection.

In alignment marker unlock state, the design did not treat each lane separately as specification defined but treat all lanes together.

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