Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.9.2. TLB Features

The main TLB has the following features:

  • Lockable entries using the lock‑by‑entry model
  • Supports hardware page table walks to perform look‑ups in the L1 data cache

The MPU address map is divided into the following regions:

  • The boot region
  • The SDRAM region
  • The FPGA slaves region
  • The HPS peripherals region
Note: The SMP bit in the ACTLR register must be set before enabling the MMU.