Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.3. I2C Controller Signal Description

All instances of the I2C controller connect to external pins through pin multiplexers. Pin multiplexing allows all instances to function simultaneously and independently. The pins must be connected to a pull-up resistors and the I2C bus capacitance cannot exceed 400 pF.

There are five instances of the I2C which can be routed to the HPS I/O pins. Three of these I2C modules can be used for PHY management by the three Ethernet Media Access Controllers within the HPS. For more information about routing the I2C signals to the FPGA and HPS I/O pins, refer to the HPS Component Interfaces chapter.

Table 216.  I2C Controller Interface HPS I/O Pins

Pin Name

Signal Width

Direction

Description

SCL

1 bit

Bidirectional

Serial clock

SDA

1 bit

Bidirectional

Serial data

Table 217.  HPS I2C Signals for FPGA Routing

Signal Name

Signal Width

Direction

Description

i2c<#>_scl

1 bit

Input

Incoming I2C clock source. This is the input SCL signal

i2c<#>_out_clk

1 bit

Output

Outgoing I2C clock enable. Output SCL signal. This signal is logically inverted and is synchronous to the HPS peripheral clock

i2c<#>_sda

1 bit

Input

Incoming I2C data. This is the input SDA signal.

i2c<#>_out_data

1 bit

Output

Outgoing I2C data enable. Output SDA signal. This signal is logically inverted and is synchronous to the HPS peripheral clock.

Figure 124. I2C Interface in FPGA Fabric


The figure above shows the typical connection on the I2C interface in FPGA fabric with alt_iobuff.

For both I2C clock and data, external IO pins are open drain connection. When output enables i2c_out_data and i2c_out_clk are asserted, external signal will be driven to ground.