Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

2.2.2. Cortex-A9 MPCore

The MPU subsystem is a stand-alone, full-featured Arm* Cortex*-A9 MPCore* dual-core 32-bit application processor. It provides the following functionality:

  • Arm* Cortex*-A9 MPCore*
    • Two Arm* Cortex*-A9 processors
    • NEON* single instruction, multiple data (SIMD) coprocessor and vector floating-point v3 (VFPv3) per processor
    • Snoop control unit (SCU) to ensure coherency between processors
    • Accelerator coherency port (ACP) that accepts coherency memory access requests
    • Interrupt controller
    • One general-purpose timer and one watchdog timer per processor
    • Debug and trace features
    • 32 KB instruction and 32 KB data level 1 (L1) caches per processor
    • Memory management unit (MMU) per processor
  • Arm* L2-310 level 2 (L2) cache
    • Shared 512 KB L2 cache

As shown in the "HPS Block Diagram", the L2 cache has one 64-bit master port that is connected to the main L3 interconnect and one 64-bit master port connected to the SDRAM L3 interconnect. A programmable address filter in the L2 cache controls which portions of the 32-bit physical address space can be accessed by each master.