Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

6.3.2.1. DMA Controller

The security state of the DMA controller is controlled by the manager thread security (mgr_ns) and interrupt security (irq_ns) bits of the DMA register.

The periph_ns register bits determine if a peripheral request interface is secure or non-secure.

Note: The periph_ns register bits must be configured before the DMA is released from global reset.