Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

30.15.1. HPS Conduit Interfaces Connecting to the HPS I/O

The Pin Mux and Peripherals interface, hps_io, is connected to an Intel® Platform Designer (Standard) conduit BFM for simulation. Platform Designer (Standard) configures the BFM as shown in the following tables:

Table 279.  PLL Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 .. 5 N/A hps_io_phery_cm_PLL_CLK0 () .. hps_io_phery_cm_PLL_CLK4 ()
Table 280.  SD/MMC Interface Simulation ModelThis peripheral is a boot source.
To HPS I/Os Options Signal(s)
1

SDMMC bit-width = Default (1)

SDMMC Power Enable = Yes

hps_io_phery_sdmmc_CMD()

hps_io_phery_sdmmc_PWR_ENA(), only when SDMMC Power Enable option is set to "Yes"

hps_io_phery_sdmmc_D0()

hps_io_phery_sdmmc_CCLK ()

SDMMC bit-width = 4

SDMMC Power Enable = Yes61

The same signal list from above with SDMMC bit-width set to "default", plus the following signals:

hps_io_phery_sdmmc_D1()

hps_io_phery_sdmmc_D2()

hps_io_phery_sdmmc_D3()

SDMMC bit-width = 8

SDMMC Power Enable = Yes61

The same signal list from above with SDMMC bit-width set to 4, plus the following signals:

hps_io_phery_sdmmc_D4()

hps_io_phery_sdmmc_D5()

hps_io_phery_sdmmc_D6()

hps_io_phery_sdmmc_D7()

Table 281.  USB Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_usb1_DATA0 ()

hps_io_phery_usb1_DATA1 ()

hps_io_phery_usb1_DATA2 ()

hps_io_phery_usb1_DATA3 ()

hps_io_phery_usb1_DATA4 ()

hps_io_phery_usb1_DATA5 ()

hps_io_phery_usb1_DATA6 ()

hps_io_phery_usb1_DATA7 ()

hps_io_phery_usb1_CLK ()

hps_io_phery_usb1_STP ()

hps_io_phery_usb1_DIR ()

hps_io_phery_usb1_NXT ()

2

hps_io_phery_usb0_DATA0 ()

hps_io_phery_usb0_DATA1 ()

hps_io_phery_usb0_DATA2 ()

hps_io_phery_usb0_DATA3 ()

hps_io_phery_usb0_DATA4 ()

hps_io_phery_usb0_DATA5 ()

hps_io_phery_usb0_DATA6 ()

hps_io_phery_usb0_DATA7 ()

hps_io_phery_usb0_CLK ()

hps_io_phery_usb0_STP ()

hps_io_phery_usb0_DIR ()

hps_io_phery_usb0_NXT ()

Add the same signal list from above to this list of signals.

Table 282.  EMAC Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1

EMAC A is available for selecting options. See the signals in the "Signal(s)" column.

RGMII? = RMII and PHY Options = None (Default List)

Note: Where <i> is "To HPS I/Os" - 1.

hps_io_phery_emac<i>_TX_CLK ()

hps_io_phery_emac<i>_TXD0 ()

hps_io_phery_emac<i>_TXD1 ()

hps_io_phery_emac<i>_RX_CTL ()

hps_io_phery_emac<i>_TX_CTL ()

hps_io_phery_emac<i>_RX_CLK ()

hps_io_phery_emac<i>_RXD0 ()

hps_io_phery_emac<i>_RXD1 ()

When RGMII? = RGMII

Add the following signals to the Default List:

hps_io_phery_emac<i>_TXD2 ()

hps_io_phery_emac<i>_TXD3 ()

hps_io_phery_emac<i>_RXD2 ()

hps_io_phery_emac<i>_RXD3 ()

When PHY Options = MDIO

Add the following signals to the Default List:

hps_io_phery_emac<i>_MDIO ()

hps_io_phery_emac<i>_MDC ()

When PHY Options = I2C

Add the following signals to the Default List:

hps_io_phery_i2cemac<i>_SDA ()

hps_io_phery_i2cemac<i>_SCL ()

2

EMAC A and EMAC B are available for selecting options. See the signals in the "Signal(s)" column.

This signal list is comprised of the list for when "To HPS I/Os" is equal to 1, taking in to consideration the various options, plus the following:
Note: Where <i> is "To HPS I/Os" - 1.

RGMII? = RMII and PHY Options = None (Default List)

hps_io_phery_emac<i>_TX_CLK ()

hps_io_phery_emac<i>_TXD0 ()

hps_io_phery_emac<i>_TXD1 ()

hps_io_phery_emac<i>_RX_CTL ()

hps_io_phery_emac<i>_TX_CTL ()

hps_io_phery_emac<i>_RX_CLK ()

hps_io_phery_emac<i>_RXD0 ()

hps_io_phery_emac<i>_RXD1 ()

When RGMII? = RGMII

Add the following signals to the Default List:

hps_io_phery_emac<i>_TXD2 ()

hps_io_phery_emac<i>_TXD3 ()

hps_io_phery_emac<i>_RXD2 ()

hps_io_phery_emac<i>_RXD3 ()

When PHY Options = MDIO

Add the following signals to the Default List:

hps_io_phery_emac<i>_MDIO ()

hps_io_phery_emac<i>_MDC ()

When PHY Options = I2C

Add the following signals to the Default List:

hps_io_phery_i2cemac<i>_SDA ()

hps_io_phery_i2cemac<i>_SCL ()

3

EMAC A, EMAC B, and EMAC C are available for selecting options. See the signals in the "Signal(s)" column.

This signal list is comprised of the list for when "To HPS I/Os" is equal to 1 and 2, taking in to consideration the various options, plus the following:
Note: Where <i> is "To HPS I/Os" - 1.

RGMII? = RMII and PHY Options = None (Default List)

hps_io_phery_emac<i>_TX_CLK ()

hps_io_phery_emac<i>_TXD0 ()

hps_io_phery_emac<i>_TXD1 ()

hps_io_phery_emac<i>_RX_CTL ()

hps_io_phery_emac<i>_TX_CTL ()

hps_io_phery_emac<i>_RX_CLK ()

hps_io_phery_emac<i>_RXD0 ()

hps_io_phery_emac<i>_RXD1 ()

When RGMII? = RGMII

Add the following signals to the Default List:

hps_io_phery_emac<i>_TXD2 ()

hps_io_phery_emac<i>_TXD3 ()

hps_io_phery_emac<i>_RXD2 ()

hps_io_phery_emac<i>_RXD3 ()

When PHY Options = MDIO

Add the following signals to the Default List:

hps_io_phery_emac<i>_MDIO ()

hps_io_phery_emac<i>_MDC ()

When PHY Options = I2C

Add the following signals to the Default List:

hps_io_phery_i2cemac<i>_SDA ()

hps_io_phery_i2cemac<i>_SCL ()

Table 283.  SPIM Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_spim0_CLK ()

hps_io_phery_spim0_MOSI ()

hps_io_phery_spim0_MISO ()

hps_io_phery_spim0_SS0_N ()

2

The same list as above plus the following signals:

hps_io_phery_spim1_CLK ()

hps_io_phery_spim1_MOSI ()

hps_io_phery_spim1_MISO ()

hps_io_phery_spim1_SS0_N ()

Table 284.  SPIS Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_spis0_CLK ()

hps_io_phery_spis0_MOSI ()

hps_io_phery_spis0_MISO ()

hps_io_phery_spis0_SS0_N ()

2

The same list as above plus the following signals:

hps_io_phery_spis1_CLK ()

hps_io_phery_spis1_MOSI ()

hps_io_phery_spis1_MISO ()

hps_io_phery_spis1_SS0_N ()

Table 285.  UART Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_uart0_RX ()

hps_io_phery_uart0_TX ()

hps_io_phery_uart0_CTS_N ()

hps_io_phery_uart0_RTS_N ()

2

The same list as above plus the following signals:

hps_io_phery_uart1_RX ()

hps_io_phery_uart1_TX ()

hps_io_phery_uart1_CTS_N ()

hps_io_phery_uart1_RTS_N ()

Table 286.  I2C Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_i2c0_SDA ()

hps_io_phery_i2c0_SCL ()

2

The same list as above plus the following signals:

hps_io_phery_i2c1_SDA ()

hps_io_phery_i2c1_SCL ()

Table 287.  NAND Interface Simulation ModelThis peripheral is a boot source.
To HPS I/Os Options Signal(s)
1 NAND bit-width = 8

hps_io_phery_nand_ALE ()

hps_io_phery_nand_CE_N ()

hps_io_phery_nand_CLE ()

hps_io_phery_nand_RE_N ()

hps_io_phery_nand_RB ()

hps_io_phery_nand_ADQ0 ()

hps_io_phery_nand_ADQ1 ()

hps_io_phery_nand_ADQ2 ()

hps_io_phery_nand_ADQ3 ()

hps_io_phery_nand_ADQ4 ()

hps_io_phery_nand_ADQ5 ()

hps_io_phery_nand_ADQ6 ()

hps_io_phery_nand_ADQ7 ()

hps_io_phery_nand_WP_N ()

hps_io_phery_nand_WE_N ()

NAND bit-width = 16

The same list as above plus the following signals:

hps_io_phery_nand_ADQ8 ()

hps_io_phery_nand_ADQ9 ()

hps_io_phery_nand_ADQ10 ()

hps_io_phery_nand_ADQ11 ()

hps_io_phery_nand_ADQ12 ()

hps_io_phery_nand_ADQ13 ()

hps_io_phery_nand_ADQ14 ()

hps_io_phery_nand_ADQ15 ()

Table 288.  TRACE Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 N/A

hps_io_phery_trace_CLK ()

hps_io_phery_trace_D0 ()

hps_io_phery_trace_D1 ()

hps_io_phery_trace_D2 ()

hps_io_phery_trace_D3 ()

Table 289.  GPIO Pins Interface Simulation Model
To HPS I/Os Options Signal(s)
1 .. 62 N/A

hps_io_gpio_gpio2_io0 () .. hps_io_gpio_gpio2_io62 ()

Table 290.  QSPI Interface Simulation ModelThis peripheral is a boot source.
To HPS I/Os Options Signal(s)
1 N/A
Note: Although there are no options for this peripheral, "Boot" must be selected also for the signals to become available.

hps_io_phery_qspi_IO0()

hps_io_phery_qspi_IO1()

hps_io_phery_qspi_IO2_WPN()

hps_io_phery_qspi_IO3_HOLD()

hps_io_phery_qspi_CLK ()

hps_io_phery_qspi_SS0()

61 When SDMMC Power Enable is set to Default, the hps_io_phery_sdmmc_PWR_ENA() signal is not available.