Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.9.2.2. SDRAM Adapter Interrupt Support

The SDRAM adapter supports the following three interrupts:

  • The status interrupt occurs when:
    • Calibration is complete.
    • The ECC is unable to schedule an auto-correction write-back to memory. This occurs only when the auto-write-back FIFO is full.
  • The ECC read-back interrupt occurs when an ECC single-bit error is detected in the read data. When this happens, the return data is corrected and returned to the NoC.
  • The double-bit or fatal error interrupt occurs when any of the following three errors happens:
    • A double-bit error in the read data has been detected, which cannot be corrected.
    • A single-bit error has been detected in the address field. This means that the data that the adapter is returning has no bit errors, but is not the requested data. When this happens, the adapter returns a data error along with the data.
    • Any of the DDR4 devices have triggered their ALERT pins.
      • Address or command parity check has failed
      • Write data CRC check has failed
      • Cannot gracefully recover because SDRAMs are not providing feedback on failure case