Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

27.5.1.3. Resets

There are two ways that the SDRAM controller can be connected to reset.

  • One way - Reset and status connection is automatic by just connecting the SDRAM Hard Memory Controller (HMC) to the HPS. You access these wires in the reset manager so that you can reset the HMC and find out when the reset is complete.
  • Second way - The HMC reset input from the FPGA fabric. This signal is called global_reset_n and is one of the signals exposed to the FPGA fabric from the HMC when you instantiate it in Platform Designer (Standard). The purpose of this signal is to reset the HMC from the FPGA side of the fabric. Before the FPGA fabric is configured, the memory controller ignores this signal which is why the memory controller can become live before the fabric is configured. This also means that the user design that gets configured into the fabric must drive it because once the fabric is configured, the HMC uses global_reset_n as an input source.
Note: You must connect the input source for global_reset_n to the cold reset input for the HPS. If you put the SDRAM into reset but that same reset source does not connect to the HPS, the memory is then wiped out while the HPS is still trying to access it. This causes the software to crash.