AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Recommended PCB Design Guideline at the CFP2/CFP4 Connector

Figure 53. Recommended CFP2/CFP4 Connector Layout on the PCB

Intel recommends that you observe the following design guidelines:

  • For CFP4: rectangular (W=62 mil x H=60 mil) cutout on both layers GND02/GND04 1 under the CFP4 pads
  • Signal and GND vias, drill diameter = 10 mil, Via pad diameter = 20 mil
    • All signal vias are back-drilled
    • Each signal via must have one single GND via
  • Signal anti-pads: T = 90 mil, R = 22.5 mil
  • G (Signal-to-GND via pitch) = 30 mil
Figure 54. Recommended CFP2/CFP4 Connector Fan-out Routing on the PCBRouting layers are differentiated by different colors.

The differential lanes in green can be routed on any signal layer.

The differential lanes in blue can only be routed on signal layers where the GND reference layers are not GND02/GND04 because they cross the cutout area under the connector. You can route these lanes from the opposite direction (similar to the green lanes) if there is space for routing. In this case, all signal layers can be used for signal routing.

Make sure that you have proper GND reference plane for signal routing.

Observe these CFP2/CFP4 guidelines for better performance at 28 Gbps on the main channel:

  • Match the length for each pair (between P and N lanes). Both P and N lanes must be in phase to recover the data. The skew matching in a pair is 2 ps.
  • Length matching between pairs is not mandatory unless it is specified by designers.
  • For optimized FPGA break-out layout design, refer to FPGA Fan-out Region chapter.
  • Always use minimal routing length from the FPGA to the connector to achieve minimum insertion loss. Refer to PCB Stackup Selection Guideline chapter for Stackup and material selection and Recommendations for High Speed Signal PCB Routing chapter for HSSI PCB routing.
  • Ensure that the insertion loss and return of the channel is within specifications. Refer to Electrical Specifications chapter for specifications.
Related Information
1 This refers to the first and second GND layers under the connector. If the stack-up height is less than 1:12, you can also use an 8 mil finished via drill and 18 mil via pad.
Note: The actual drill is 10 mil, but the copper filling inside makes it an 8 mil finished drill.
Intel recommends that you have both the signal via and GND via located closely enough to the connectors' signal and GND pads, respectively, to avoid cavity resonance and higher frequencies.
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