AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.4.5. Using the Reset Release Intel® FPGA IP

During the device configuration, the global configuration control signals hold the core fabric in a frozen state to prevent electrical contention. Sectors that comprise multiple logic array block (LAB) rows are all asynchronously unfrozen by different Local Sector Managers (LSM). Within each sector, LAB rows and registers are released sequentially by each LSM. Consequently, different logic can operate while other logic remains frozen during the process.

If the activity of the logic partly becomes operational, this could potentially cause some control logic or state machines without a reset strategy to enter an illegal or unknown state, once the entire fabric goes into the user mode.

Therefore, after every compile, the Intel® Quartus® Prime software generates the following critical warning message: 

Use the Reset Release IP in Intel Stratix 10 FPGA
 designs to ensure a successful configuration. For more information about the 
Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.
The Design Assistant report in the Synthesis folder also includes RES-10204 rule violation - Reset Release Instance Count Check.
Figure 32. RES-10204 Rule Violation - Reset Release Instance Count Check

Design Assistant categorizes the lack of Reset Release Intel® FPGA IP as HIGH severity. Without the IP, intermittent functional issues could result on every design power-up.

The Reset Release IP can hold the design at reset until the device has fully entered the user mode. You can specify two options to signal the safe entry to the user mode:
  • Using the INIT_DONE output PIN signal
  • Using the nINIT_DONE output from the Reset Release IP

Refer to the Related Information for detailed information about connecting your design with the Reset Release Intel® FPGA IP.

Designs commonly use the PLL lock signal to hold the design logic in reset until the PLL is locked. To make sure that the lock happens after the device completes initialization, you must gate the PLL reset input with nINIT_DONE, as shown in the following figure.
Figure 33. Using nINIT_DONE on PLL_Reset Signal to Generate System nReset
Related Information
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