AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.4.6.1. C-Cycle Equivalence

The c-cycle refers to the number of clock cycles a design requires after power-up to ensure functional equivalence. The c-cycle value is an important consideration in structuring the reset sequence of your design.

Consider the following simple circuit where register F1 at power-up can have either state ‘0’ or state ‘1’. Assuming the clouds of logic are purely combinational, there are 2 possible states in the circuit, F1 = ‘0’ or F1 = ‘1’.
Figure 34. Circuit Before Retiming
If the retimer pushes F1 forward, then the register is duplicated in each branch that F1 drives.
Figure 35. Register Duplicated
After retiming and register duplication, the circuit now has four possible states at power-up. The addition of two potential states in the circuit after retiming, potentially changes the deign functionality.
Table 2.  Registers F11 and F12 States
F11 States F12 States
0 0
0 1
1 0
1 1

Apply an extra clock cycle after power-up to ensure the functional equivalence of the design after retiming. The extra cycle ensures that the states of F11 and F12 are always identical resulting in two possible states for the registers, 0/0 or 1/1, assuming the combinational logic is non-inverting on both paths.

Backward retiming is always a safe operation with c-cycle value of 0. The Compiler always permits merging if you do not specify initial conditions for F11 and F12. If you specify initial conditions, the Compiler accounts for those initial states and retiming transformation occurs only if the initial states are preserved.

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