AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication

The DUPLICATE_HIERARCHY_DEPTH assignment uses design hierarchy information to guide the creation of duplicates and their fan-out assignments during synthesis. 

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to <register_name> <num_levels>

Where register_name is the last register in a chain that fans out to multiple hierarchies. To create a register tree, ensure that there are sufficient simple registers behind the node, and those simple registers are automatically pulled into the tree.

num_levels corresponds to the upper bound of the number of registers that exist in the chain, to use for duplicating down the hierarchies.

The registers in the chain must satisfy all the following conditions to be included in duplication:

  • Registers must be fed only by another register and cannot be fed by combinational logic.
  • Registers cannot be part of a synchronizer chain.
  • Registers cannot have any secondary signals.
  • Registers cannot have a preserve attribute or a PRESERVE_REGISTER assignment.
  • All registers in the chain except the last one must have only one fan-out.

Consider the following design with pipeline registers regA, regX, regY, and regZ added after the reset synchronizer block:

Figure 26. Pipeline Registers Added to Reset Synchronizer Block 
set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 1

When num_levels is set to 1, only regZ is pulled out of the chain and pushed down by one hierarchy level into its fan-out tree.

Figure 27. num_levels set to 1 
set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 2

When num_levels is set to 2, both regY and regZ are pulled out of the chain. regZ stops at the maximum hierarchy depth 2 and regY stops at hierarchy depth 1.

Figure 28. num_levels is set to 2 
set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 3

When num_levels is set to 3, regX, regY, and regZ are pulled out of the chain and pushed to a maximum depth of 1, 2, and 3 levels respectively.

Figure 29. num_levels is set to 3

The Synthesis report includes the Hierarchical Tree Duplication Summary report that provides information on the registers impacted by the DUPLICATE_HIERARCHY_DEPTH assignment. You can refer to the report to set or modify the assignments and further improve the results.

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