AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.1.2. Hyper-Registers Require Synchronous Reset

For the best performance, avoid resets except when necessary. When design conditions require a reset, you must decide the type of reset to use, asynchronous or synchronous.

The Hyper-Retiming feature facilitates movement between registers to balance the propagation delays between them, with the aim of fixing critical path timing. Hyper-Retiming moves the ALM registers into the Hyper-Register locations that are available in every routing segment of the fabric.

By design, the Hyper-Registers do not have asynchronous resets. Therefore, the Intel® Quartus® Prime Fitter cannot retime ALM registers with an asynchronous reset into a Hyper-Register location. Instead, use a synchronous reset to permit the usage of the Hyper-Registers during retiming. The ability to retime into Hyper-Registers helps achieve the best possible performance.

In blocks where the use of asynchronous resets is unavoidable, minimize the use of asynchronous resets within these blocks wherever possible. Asynchronous resets allow a circuit to reset with or without a clock signal present. There may be blocks that require this function, including any of the following:

  • Clock source and distribution circuitry
  • Power management block
  • System reset generator

Use synchronous resets if a clock is present on every reset assertion. You may be able to use asynchronous resets for blocks using slow clocks when timing is not critical, especially if the asynchronous reset helps in decongesting data path routing.

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