Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.10.1.1. Read and Write Address Channels

Most signals are allowed. However, the following limitations are present in Platform Designer 14.0:

  • Supports 64-bit addressing.
  • ID width limited to 18-bits.
  • HPS-FPGA host interface has a 12-bit ID.