Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.3.3.1. Avalon® Data Pattern Generator IP Control and Status Registers

Table 137.   Avalon® Data Pattern Generator IP Control and Status Register MapEach register is 32-bits wide.
Offset Register Name
base + 0 status
base + 1 control
base + 2 fill
Table 138.   Avalon® Data Pattern Generator IP Status Register Bits
Bits Name Access Description
[15:0] ID RO A constant value of 0x64.
[23:16] NUMCHANNELS RO The configured number of channels.
[30:24] NUMSYMBOLS RO The configured number of symbols per beat.
[31] SUPPORTPACKETS RO A value of 1 indicates data packet support.
Table 139.   Avalon® Data Pattern Generator IP Control Register Bits
Bits Name Access Description
[0] ENABLE RW Setting this bit to 1 enables the data pattern generator IP.
[7:1] Reserved
[16:8] THROTTLE RW

Specifies the throttle value which can be between 0–256, inclusively. The Data Pattern Generator IP uses this value in conjunction with a pseudo-random number generator to throttle the data generation rate.

[17] SOFT RESET RW When this bit is set to 1, all internal counters and statistics are reset. Write 0 to this bit to exit reset.
[31:18] Reserved
Table 140.   Avalon® Data Pattern Generator IP Fill Register Bits
Bits Name Access Description
[0] BUSY RO A value of 1 indicates that data transmission is in progress, or that there is at least one command in the command queue.
[6:1] Reserved
[15:7] FILL RO The number of commands currently in the command FIFO.
[31:16] Reserved