Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.15. Preserving System Elements for Debug

The Compiler optimizes the module, interface, and port names in your Platform Designer system during synthesis and place-and-route. Unless preserved, the module, interface, and port names in your system may not exist in the post-fit netlist after optimizations. For example, synthesis can merge duplicate registers, or add tildes (~) to net names that fan-out from a node.

You can use any of the following methods to prevent synthesis from performing optimizations on specific modules, interfaces, or port names, allowing the names to persist into the post-fit netlist for Signal Tap and other debug monitoring.

  1. Enable preserve for debug using any of the following methods:
    • On the System View tab, right-click any module, interface or port, and click Preserve for Debug in the context menu.
    • On the Filter tab, right-click any module, interface, or port, and click Preserve for Debug in the context menu. A green icon color in the Filter tab indicates that preservation is applied.
    Applying Preserve for Debug adds corresponding assignments to the .qip. Once applied, you can verify the assignments are correct in the .qip.
  2. Recompile the design to apply the Preserve for Debug and view the preserved nodes following compilation.
Figure 72. Preserve for Debug from System View
Note: For more information about preserving signals, refer to Preserving Registers During Synthesis, in Intel® Hyperflex® Architecture High-Performance Design Handbook. Specifying preservation synthesis attributes may increase device resource utilization or decrease timing performance when the attribute is active.