Intel® Stratix® 10 MX FPGA Development Kit User Guide

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ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.9.2. Power Distribution System

Figure 15. Power Distribution System Block Diagram
Table 28.  Power Supply List
Power Source Name Power Name Maximum Output Current (A) Description
LTC3884 (U44)

VCC (0.85V)

VCCP (0.85V)

 132

Core Logic Power

Periphery Power
EM2120L (U51) VCCIO_UIB (1.2V) 12 Power for HBM’s Universal Interface Block
EN63A0 (U46)

S10_VCCERAM (0.9V)

VCCPLLDIG_SDM (0.9V)

 4.6 Embedded memory and digital transceiver power
EN63A0 (U49) S10_VCCT_GXB (1.12V) 2.1 Transmitter Power
EN63A0 (U48) S10_VCCRR_GXB (1.12V) 4.0 Receiver Power Right side
EN63A0 (U47) S10_VCCRL_GXB (1.12V) 4.0 Receiver Power Left side
EN63A0 (U50)

VCCH_GXB(1.8V)

VCCADC (1.8V)

VCCA_PLL (1.8V)

VCC_PLL_SDM (1.8V)

VCCPT (1.8V)

VCCBAT (1.8V)

VCCIO_SDM (1.8V)

VCCIO (1.8v)

11

Analog power for Receivers

ADC power

PLL Analog Global power

PLL Power to SDM block

Charge-pump power

Battery Back-up power for encryption key

Configuration pins power

IO Power
LTM4625 (U40) 5V 5.0 System 5V Rail
EY1501 (U41) 3V3_STBY (3.3V)
EY1501 (U42) 1p8V_PRE_STBY (1.8V)
EN6337 (U58)

2p5V (2.5V)

DDR4_VCCP (2.5V)

DDR4_VCCSPD (2.5V)

 1.0 System 2.5V Rail
EN6362 (U57) HiLo VDD (1.25V/1.30V/1.35V/1.5V) 6.0 VDD power for HiLo
EN6362 (U56) HiLo VDDQ (1.25V/1.30V/1.35V/1.5V) 2.0 VDDQ power for HiLo
EN6360 (U60) VCCM (2.5V) 2.6 Embedded HBM2 memory power
EM2130H(U43) 3p3V (3.3V) 30 System 3.3V rail
TPS51200 (U54) 0p6V_DDR4_DIMM_VTT (0.6V) 1mA Termination power for DIMM
TPS51200 (U55) 0p6V_DDR4_COMP_VTT (0.6V) 1mA Termination power for on-board DDR4
12V_G1, 12V_G2 12V 20 System 12V rail
Level Two Title