Intel® Stratix® 10 MX FPGA Development Kit User Guide

Download PDF
ID 683867
Date 6/15/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Components Overview 4.2. Intel® MAX® 10 FPGA System Controller 4.3. Intel® MAX® 10 FPGA Power Manager 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Interfaces and Ports 4.7. HiLo Daughter Cards 4.8. Clocks 4.9. Power
4.6. Interfaces and Ports x
4.6.1. PCI Express 4.6.2. Memory Interface 4.6.3. High Bandwidth Memory (HBM2) 4.6.4. QSFP 4.6.5. I2C Flash Memory
4.6.2. Memory Interface x
4.6.2.1. On-board DDR4 Memory Interface 4.6.2.2. DDR4/DDR-T DIMM Memory Interface 4.6.2.3. HiLo Memory Interface
4.7. HiLo Daughter Cards x
4.7.1. DDR4 4.7.2. QDR-IV
4.9. Power x
4.9.1. Power Guidelines 4.9.2. Power Distribution System 4.9.3. Power Sequence 4.9.4. Power Measurement 4.9.5. Power Fast Discharging 4.9.6. Thermal Limitations and Protection 4.9.7. Cooling Design 4.9.8. Mechanical Information 4.9.9. Top Cover Removal
5. Board Test System x
5.1. Preparing the Board Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The Sys Info Tab 5.3.3. The QSFP Tab 5.3.4. The PCIE Tab 5.3.5. The Component DDR4 Tab 5.3.6. The HiLo DDR4 Tab 5.3.7. The DDR4 Dimm Tab 5.3.8. The HBM2 Top Tab 5.3.9. The HBM2 Bottom Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in the QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Statement
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.8. Clocks

Figure 14.  Intel® Stratix® 10 MX FPGA Development Kit Clock Inputs and Default Frequencies
Table 27.  On-board Clocks
Source Schematic Signal Name Default Frequency I/O Standard Intel® Stratix® 10 FPGA Pin Number Application
U16 REFCLK_ZQSFP0_P 644.53125 MHz LVDS AJ43 QSFP0 Reference Clock
REFCLK_ZQSFP0_N 644.53125 MHz LVDS AJ42
REFCLK_ZQSFP1_P 644.53125 MHz LVDS AJ9 QSFP1 Reference Clock
REFCLK_ZQSFP1_N 644.53125 MHz LVDS AJ10
CLK_UIB0_P 100 MHz LVDS AR26 UIB0 Reference Clock
CLK_UIB0_N 100 MHz LVDS AP26
CLK_UIB1_P 100 MHz LVDS P27 UIB1 Reference Clock
CLK_UIB1_N 100 MHz LVDS R27
CLK_ESRAM0_P 100 MHz LVDS AU31 ESRAM0 Reference Clock
CLK_ESRAM0_N 100 MHz LVDS AU32
CLK_ESRAM1_P 100 MHz LVDS V31 ESRAM1 Reference Clock
CLK_ESRAM1_N 100 MHz LVDS U31
CLK_SYS_100M_P 100 MHz LVDS AU17 System Clock
CLK_SYS_100M_N 100 MHz LVDS AU16
REFCLK_PCIE_RT_P 100 MHz LVDS AW9 PCIe* Root Port Reference Clock
REFCLK_PCIE_RT_N 100 MHz LVDS AW10
REFCLK_PCIE_EP_P 100 MHz LVDS AW43 PCIe* End Point Reference Clock
REFCLK_PCIE_EP_N 100 MHz LVDS AW42
U18 CLK_SYS_50M_P 50 MHz LVDS BE17 FPGA Clocks
CLK_SYS_50M_N 50 MHz LVDS BD17
CLK_CORE_BAK_P 100 MHz LVDS AT13 FPGA Core Clocks
CLK_CORE_BAK_N 100 MHz LVDS AU13
S10_OSC_CLK_1 125 MHz LVCMOS AR35 Configuration Clock
REFCLK_PCIE_EP1_N 100 MHz LVDS BA42 PCIe* Transceivers Clock
REFCLK_PCIE_EP1_P 100 MHz LVDS BA43
U19 CLK_HILO_MEM_N 133.333 MHz LVDS AY31 HiLo Memory Clocks
CLK_HILO_MEM_P 133.333 MHz LVDS AW31
CLK_DDR4_COMP_N 133.333 MHz LVDS B41 On-board DDR4 Memory clocks
CLK_DDR4_COMP_P 133.333 MHz LVDS A42
CLK_DDR4_DIMM_N 133.333 MHz LVDS C18 DIMM Module Clocks
CLK_DDR4_DIMM_P 133.333 MHz LVDS B18
Level Two Title