AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Test Procedure

Follow these steps to test the design examples in hardware:

  1. Run the following command in the system console to start the test.

    TEST_EXT_LB <channel> <speed> <burst_size>

    Example: TEST_EXT_LB 0 2.5G 1000000000

    Table 3.  Command Parameters
    Parameter Valid Values Description
    channel 0, 1 The channel number to test.
    speed 1G, 2.5G The PHY speed.
    burst_size An integer value The number of packets to generate for the test.
  2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
    Figure 9. Sample Test Output—Ethernet Packet Monitor
    Figure 10. Sample Test Output—Statistics Counters
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