AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples

Document Version Changes
2018.12.11
  • Renamed the document as AN 757: 1G/2.5G Ethernet Design Examples.
  • Updated the Hardware and Software Requirements topic.
  • Corrected a broken link to the design files in the Using the Design Example topic.
  • Made minor editorial updates to the document.
Date Version Changes
June 2017 2017.06.19
  • Rebranded to Intel.
  • Changed Intel® Arria® 10 references to Arria® V.
May 2016 2016.05.20
  • Updated the Hardware Setup diagram.
  • Added Arria V support.
February 2016 2016.02.05 Initial release
Level Two Title