AN 757: 1G/2.5G Ethernet Design Examples

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ID 683753
Date 11/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 757: 1G/2.5G Ethernet Design Examples
AN 757: 1G/2.5G Ethernet Design Examples x
Features Hardware and Software Requirements Functional Description Using the Design Example Simulation Hardware Testing Interface Signals Configuration Registers Document Revision History for AN 757: 1G/2.5G Ethernet Design Examples
Functional Description x
Design Components Reset Scheme Clocking Scheme
Simulation x
Testbench Using the Simulator Test Case—Design Example without the IEEE 1588v2 Feature
Hardware Testing x
Setup Test Procedure
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals TOD Interface Signals
Configuration Registers x
Transceiver Reconfiguration
AN 757: 1G/2.5G Ethernet Design Examples

Clock and Reset Interface Signals

Table 4.   Clock and Reset Interface Signals
Signal Direction Width Description
csr_clk In 1 125-MHz configuration clock for the Avalon-MM interface.
mac_clk In 1 156.25-MHz clock for the Avalon-ST interface. This clock must have 0 ppm frequency difference to refclk.
refclk In 1 125-MHz reference clock for the TX PLLs.
rx_pma_clkout Out 1 Recovered clock from CDR.
reset In 1 Asserting this signal resets the whole design example. Asynchronous and active low signal.
tx_digital_reset Out 2 Asserting this signal resets the TX datapath. Asynchronous and active low signal.
rx_digital_reset Out 2 Asserting this signal resets the RX datapath. Asynchronous and active low signal.
Level Two Title