Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.9.7. I2C/PMBUS

The power and various peripherals are managed by I2C/PMBUS. The topology of the I2C bus is shown in the figure below.

Figure 8. I2C Bus Topology
Level Two Title