Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.4. FPGA Configuration

JTAG

The JTAG topology of the board is shown in the figure below. An on-board USB Blaster is implemented with the Intel® MAX® 10. It is in the form of a micro-USB type-B connector (J9).

Figure 3. JTAG topology block diagram

The system Intel® MAX® 10 device itself can be configured through on-board USB port or an external USB-Blaster II header. the 2x5 header for Intel® MAX® 10 is not mounted by default.

A secondary Intel® MAX® 10 device is used for PFL configuration mode. This CFG Intel® MAX® 10 is configured with on-board USB port.

The Intel® Cyclone® 10 GX FPGA device is configured with on-board USB port or an external USB-Blaster II header.

The FMC interface also has a JTAG interface. The FMC JTAG can also be included into the JTAG chain.

The Intel® Cyclone® 10 GX device JTAG and FMC JTAG can be put included or isolated from the JTAG chain by setting a DIP switch S5.

Table 7.  JTAG DIP Switch Settings
Switch Signal Function
S5.1 FMC_JTAGEN ON - Disable JTAG
S5.2 C10_JTAGEN ON - Disable JTAG

Configuration

The Intel® Cyclone® 10 GX FPGA device can be configured using different modes. Mode selection can be done using DIP switch S1.

Table 8.  Configuration Mode Settings
Configuration Scheme VCCPGM (V) Power-On Reset Delay Valid MSEL [2:0]
JTAG-based Configuration ----- ------ Use any valid MSEL pin settings given below
AS (x1 and x4) 1.8 Fast 010
Standard 011
PS and FPP (x8, x16, x32) 1.2 / 1.5 / 1.8 Fast 000
Standard 001
Table 9.  MSEL Switch S1 Definition
Switch Signal Note
S1.1 C10_MSEL0

MSEL2 is tied to GND

ON - '0'
S1.2 C10_MSEL1
Figure 4. FPGA Configuration Scheme Block Diagram

The Intel® Cyclone® 10 GX FPGA device is configured with two modes: ASx4 or FPP x16. The AS x4 mode uses an EPCQ-L 1024 to store the image. A dedicated Intel® MAX® 10 device is used to implement PFL. It interfaces with two pieces of x16 parallel NOR flash devices to get a x32 bus width. The highest density is 2 Gb. The flash interface works at 3.3 V and various NOR flashes from different vendors can be used with this board.

Micron MT28EW01GABA1LPC-0SITES is installed in manufacturing by default. 2 Gb is provided with the board.

For the Intel® Cyclone® 10 GX FPGA device, the image size is less than 85 Mb. Multiple images can be stored and selected by the user. The image to be used can be selected with a group of Push Buttons and LEDs.

The user can select between the images to be loaded into Intel® Cyclone® 10 GX FPGA.
  • Cycling images by pushing button S7
  • CFG Intel® MAX® 10 device displays current number to be used with LEDs D16-D18
  • Initiate the reconfiguration by pushing button S12
The signal definition of these buttons and LEDs are shown below:
Table 10.  Program Selection Signals Definition
Switch / LED Signal Note
S7 PGM_SEL Select program
S12 SYS_CONFIG_PB Reconfigure
D16 PGM_LED0 PGM_LED [2:0] indicates the program to be used
D17 PGM_LED1
D18 PGM_LED2

Side Bus

A group of Side Bus signals are defined between Intel® MAX® 10 and Intel® Cyclone® 10 GX FPGA device to provide a higher speed access through on-board USB-Blaster. This interface is reserved in harwdare.

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