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1.2. Step 2: Apply Compiler Optimization Techniques
Designs that utilize a very high percentage of FPGA device resources can cause resource congestion, resulting in lower fMAX and more complex timing closure.
The Compiler's Optimization Mode settings allow you specify the focus of Compiler efforts during synthesis. For example, you optimize synthesis for Area, or Routability when addressing resource congestion. You can experiment with combinations of these same Optimization Mode settings in the Intel® Quartus® Prime Design Space Explorer II. These settings and other manual techniques can help you to reduce congestion in highly utilized designs.
Timing Closure Problem
- Designs with very high device resource utilization complicate timing closure.
Timing Closure Solutions
- Apply Compiler Optimization Modes and Strategies—specify the primary optimization mode goal for design synthesis.
- Experiment with Area and Routability Options—apply additional collections of settings to reduce congestion and meet area and routability goals.
- Consider Fractal Synthesis for Arithmetic-Intensive Designs—For high-throughput, arithmetic-intensive designs, fractal synthesis reduces device resource usage through multiplier regularization, retiming, and continuous arithmetic packing.