AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

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ID 683664
Date 2/25/2021
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Document Table of Contents
Document Table of Contents x
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition x
1.1. Step 1: Analyze and Optimize Design RTL 1.2. Step 2: Apply Compiler Optimization Techniques 1.3. Step 3: Preserve Satisfactory Results 1.4. AN 903 Document Revision History
1.1. Step 1: Analyze and Optimize Design RTL x
1.1.1. Correct Design Assistant Violations 1.1.2. Reduce Logic Levels 1.1.3. Reduce High Fan-Out Nets
1.2. Step 2: Apply Compiler Optimization Techniques x
1.2.1. Apply Compiler Optimization Modes and Strategies 1.2.2. Reduce Congestion for High Utilization
1.2.2. Reduce Congestion for High Utilization x
1.2.2.1. Experiment with Area and Routability Options 1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs
1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs x
1.2.2.2.1. Enabling or Disabling Fractal Synthesis
1.3. Step 3: Preserve Satisfactory Results x
1.3.1. Lock Down Clocks, RAMs, and DSPs 1.3.2. Preserve Design Partition Results
1.3.2. Preserve Design Partition Results x
1.3.2.1. Design Partition Settings
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition

1.4. AN 903 Document Revision History

This document has the following revision history:
Document Version Intel® Quartus® Prime Version Changes
2021.02.25 19.3 Replaced "pull" with "tension" in Analyze and Optimize Design RTL topic.
2020.03.23 19.3 Corrected syntax error in code sample in "Lock Down Clocks, RAMs, and DSPs" topic.
2019.12.03 19.3
  • First public release.
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