AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

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ID 683664
Date 2/25/2021
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Document Table of Contents x
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition x
1.1. Step 1: Analyze and Optimize Design RTL 1.2. Step 2: Apply Compiler Optimization Techniques 1.3. Step 3: Preserve Satisfactory Results 1.4. AN 903 Document Revision History
1.1. Step 1: Analyze and Optimize Design RTL x
1.1.1. Correct Design Assistant Violations Setting Up Design Assistant Running Design Assistant Viewing and Correcting Design Assistant Results 1.1.2. Reduce Logic Levels 1.1.3. Reduce High Fan-Out Nets
1.2. Step 2: Apply Compiler Optimization Techniques x
1.2.1. Apply Compiler Optimization Modes and Strategies 1.2.2. Reduce Congestion for High Utilization
1.2.2. Reduce Congestion for High Utilization x
1.2.2.1. Experiment with Area and Routability Options 1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs
1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs x
1.2.2.2.1. Enabling or Disabling Fractal Synthesis
1.3. Step 3: Preserve Satisfactory Results x
1.3.1. Lock Down Clocks, RAMs, and DSPs 1.3.2. Preserve Design Partition Results
1.3.2. Preserve Design Partition Results x
1.3.2.1. Design Partition Settings
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition

1.1.1. Correct Design Assistant Violations

Performing initial design analysis to eliminate known timing closure issues significantly increase productivity. After running an initial compilation with default settings, you can review the Design Assistant reports for initial analysis. When enabled, Design Assistant automatically reports any violations against a standard set of Intel FPGA-recommended design guidelines.

You can run Design Assistant in Compilation Flow mode, allowing you to view the violations relevant for the compilation stages you run. Alternatively, Design Assistant is available in analysis mode in the Timing Analyzer and Chip Planner.

  • Compilation Flow Mode—runs automatically during one or more stages of compilation. In this mode, Design Assistant utilizes in-flow (transient) data during compilation.
  • Analysis Mode—run Design Assistant from Timing Analyzer and Chip Planner to analyze design violations at a specific compilation stage, before moving forward in the compilation flow. In analysis mode, Design Assistant uses static compilation snapshot data.

Design Assistant designates each rule violation with one of the following severity levels. You can specify which rules you want the Design Assistant to check in your design, and customize the severity levels, thus eliminating rule checks that are not important for your design.

Design Assistant Rule Severity Levels
Categories Description Severity Level Color
Critical Address issue for hand-off. Red
High Potentially causes functional failure. May indicate missing or incorrect design data. Orange
Medium Potentially impacts quality of results for fMAX or resource utilization. Brown
Low Rule reflects best practices for RTL coding guidelines. Blue

Setting Up Design Assistant

You can fully customize the Design Assistant for your individual design characteristics and reporting requirements. Click Assignments > Settings > Design Assistant Rule Settings to specify options that control which rules and parameters apply to the various stages of design compilation for design rule checking.

Figure 2. Design Assistant Rule Settings

Running Design Assistant

When enabled, the Design Assistant runs automatically during compilation and reports enabled design rule violations in the Compilation Report. Alternatively, you can run Design Assistant in Analysis Mode on a specific compilation snapshot to focus analysis on only that stage.

To enable automated Design Assistant checking during compilation:

  • Turn on Enable Design Assistant execution during compilation in the Design Assistant Rule Settings.

To run Design Assistant in analysis mode to validate a specific snapshot against any design rules that apply to the snapshot:

  • Click Report DRC in the Timing Analyzer or Chip Planner Tasks panel.

Viewing and Correcting Design Assistant Results

The Design Assistant reports enabled design rule violations in the various stages of the Compilation Report.

Figure 3. Design Assistant Results in Synthesis, Plan, Place, and Finalize Reports
To view the results for each rule, click the rule in the Rules list. A description of the rule and design recommendations for correction appear.
Figure 4. Design Assistant Rule Violation Recommendation

Modify your RTL to correct the design rule violations.

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