Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

2.9. Programming Your FPGA Quickly Using CvP

After you verify that the host can program you FPGA device successfully, establish the CvP programming capability of your Custom Platform.
  1. Invoke the following command to generate the CvP files:
    quartus_cpf -c --cvp <revision_name>.sof <revision_name>.rbf
    You may include this command in the <your_custom_platform_name>/hardware/<board_name>/scripts/post_flow.tcl file so that it generates the CvP files automatically after each compilation.
    Your Intel® Quartus® Prime compilation directory should contain the files <revision_name>.sof, <revision_name>.periph.rbf, and <revision_name>.core.rbf files.
  2. Program the base.sof file and then reboot your machine.
  3. (Optional) You may use the Intel® Quartus® Prime Programmer to verify basic CvP functionality. Invoke the quartus_cvp command to program the base.core.rbf file.
  4. Define the contents of your fpga.bin file by adding Tcl code to the <your_custom_platform_name>/hardware/<board_name>/scripts/post_flow.tcl file that generates the fpga.bin file. Then, modify the MMD source code and the program utility so that you can use the file.
    You may use the existing format if you remove the proprietary host-to-flash programming over the cpld_bridge component from both the hardware and software.
  5. If you set the environment ACL_PCIE_FORCE_USB_PROGRAMMING earlier, unset it. Then, set the environment variable ACL_PCIE_FORCE_PERIPH_REPLACE_USB to a value of 1. Alternatively, modify the <your_custom_platform_name>/source/host/mmd/acl_pcie_device.cpp file to use CvP but not flash memory for reprogramming periphery changes. Flash programming is unavailable because of the removal of the cpld_bridge component.
  6. Navigate to the directory containing the boardtest.aocx file. Invoke the command aocl program <device_name> boardtest.aocx to reprogram the device. Confirm that the message Program succeed appears.
    Note: By default, <device_name> is the acl number. If you have retained the default naming convention, invoke the aocl program command using acl0 as <device_name>. Alternatively, if you use another naming convention for <device_name>, use that in your aocl utility command.
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