Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™

After you modify your Intel® Quartus® Prime design files, integrate your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  1. Update the <your_custom_platform_name>/hardware/<board_name>/board_spec.xml file by removing the QDR and Ethernet channels from it. Ensure that there is at least one global memory interface, and all the global memory interfaces correspond to the exported interfaces from the board.qsys Platform Designer (Standard) system file.
    QDR section of the Stratix® V Network Reference Platform's board_spec.xml file: 
    <!-- QDRII -->
<global_mem name="QDR" max_bandwidth="17600" interleaved_bytes="8"
 config_addr="0x100">
    <interface name="board" type="slave" width="64" maxburst="1"
	 address="0x200000000" size="0x1000000" latency="150" addpipe="1">
        <port name="kernel_qdr0_r" direction="r"/>
        <port name="kernel_qdr0_w" direction="w"/>
    </interface>
    <interface name="board" type="slave" width="64" maxburst="1"
	 address="0x201000000" size="0x1000000" latency="150" addpipe="1">
        <port name="kernel_qdr1_r" direction="r"/>
        <port name="kernel_qdr1_w" direction="w"/>
    </interface>
    <interface name="board" type="slave" width="64" maxburst="1"
	 address="0x202000000" size="0x1000000" latency="150" addpipe="1">
        <port name="kernel_qdr2_r" direction="r"/>
        <port name="kernel_qdr2_w" direction="w"/>
    </interface>
    <interface name="board" type="slave" width="64" maxburst="1"
	 address="0x203000000" size="0x1000000" latency="150" addpipe="1">
        <port name="kernel_qdr3_r" direction="r"/>
        <port name="kernel_qdr3_w" direction="w"/>
    </interface>
</global_mem>

    Ethernet channels section of the s5_net board_spec.xml file: 
    <channels>
    <interface name="udp_0" port="udp0_out"  type="streamsource" width="256"
	 chan_id="eth0_in"/>
    <interface name="udp_0" port="udp0_in"  type="streamsink" width="256"
	 chan_id="eth0_out"/>
    <interface name="udp_0" port="udp1_out"  type="streamsource" width="256"
	 chan_id="eth1_in"/>
    <interface name="udp_0" port="udp1_in"  type="streamsink" width="256"
	chan_id="eth1_out"/>
</channels>

  2. In the <your_custom_platform_name>/hardware/<board_name>/scripts directory, modify the post_flow.tcl file to not call the create_fpga_bin.tcl file. You can do so by commenting out the line of code containing the command call_script_as_function scripts/create_fpga_bin.tcl. 
    # Generate fpga.bin used for reprogramming
post_message "Generating fpga.bin"
if {[catch { call_script_as_function scripts/create_fpga_bin.tcl $revision_name.sof
     $revision_name.core.rbf $revision_name.periph_hash $revision_name } res]}
{
    post_message -type error "Error in create_fpga_bin.tcl! $res"
    exit 2
}
  3. Set the environment variable ACL_QSH_COMPILE_CMD to quartus_sh --flow compile top -c base.
    Setting this environment variable instructs the SDK to compile the base revision corresponding to the base.qsf file in the <your_custom_platform_name>/hardware/<board_name> directory of your Custom Platform.
  4. Perform the steps outlined in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt file to compile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl OpenCL kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the SDK installation.
    The hardware compilation stage will fail because of the absence of the fpga.bin file. However, the Intel® Quartus® Prime compilation should complete successfully and produce a boardtest.aoco Intel® FPGA SDK for OpenCL™ Offline Compiler object file.
  5. If compilation fails because of timing failures, fix the errors, or compile INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest.cl with different seeds by including the -seed=<N> option in the aoc command (for example, aoc -seed=2 boardtest.cl).
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