Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.11.3. Trigger

The Nios® V processor core supports one address or data match trigger. The trigger registers are accessible using RISC-V csr opcodes or abstract debug commands. The firing of trigger can either enter the Debug Mode or raise a breakpoint exception, which depends on the trigger registers.

Table 88.  Trigger Registers Implemented in Nios® V Processor
Name Registers Description
tselect Trigger Select Nios® V processor supports one trigger, therefore the processor selects Trigger 0 at default (value set at 0).
tdata1 Trigger Data 1 The value of type field is 2 to represent Trigger 0 as an address or data match trigger. Write behavior to tdata registers depends on the dmode field. The remaining bits acts as mcontrol.
mcontrol Match Control Controls address and data trigger implementation according to action, m, execute, store and load fields. The Nios® V processor does not implement other fields.
tdata2 Trigger Data 2 Holds trigger-specific data (virtual address, instruction opcode, data stored or loaded).
tinfo Trigger Info The value of info field is 4 at default to signify tdata1.type is 2. This implies selected trigger is an address or data match trigger.
Based on the bit field setting in mcontrol register, Nios® V processor can implement different trigger types after the selected trigger matches the tdata2 register.
Table 89.  Nios V Processor Triggers Condition and Firing Time
Triggers Condition Firing Time Exception Program Counter
Instruction Address Trigger Program Counter matches tdata2 Before executing the instruction The processor sets the Machine Exception Program Counter (mepc) to the instruction address (PC).
Instruction Opcode Trigger Instruction opcode matches tdata2 Before executing the instruction
Store Address Trigger Store address matches tdata2 After executing the store instruction The processor sets the mepc to the next instruction address (PC + 4).
Store Data Trigger Store data matches tdata2 After executing the store instruction
Load Address Trigger Load address matches tdata2 After executing the load instruction
Load Data Trigger Load data matches tdata2 After executing the load instruction
Table 90.  Address or Data Match Trigger Type
Trigger mcontrol bit fields
select execute store load
Instruction Address 0 1 0 0
Instruction Opcode 1 1 0 0
Store Address 0 0 1 0
Store Data 1 0 1 0
Load Address 0 0 0 1
Load Data 1 0 0 1
Note: The trigger is disabled in the following situations:
  • The Nios® V processor is in debug mode.
  • The Nios® V processor is in machine mode, while mcontrol.m or mcontrol.type is 0.