Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023
Public

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Document Table of Contents

2.1. Processor Performance Benchmarks

Table 2.   Nios® V/c Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Pro Edition Software
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 303 413 0.226 0.173
Intel® Arria® 10 336 410
Intel® Stratix® 10 368 441
Intel Agilex® 7 449 427
Table 3.  Benchmark Parameters for Intel® Quartus® Prime Pro Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 23.4.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/c processor core (without debug module and internal timer).
  • 128 KB on-chip memory for the instruction and data bus.
  • JTAG UART Intel® FPGA IP.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32i -mabi=ilp32
Table 4.   Nios® V/c Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Standard Edition Software
FPGA Used fMAX (MHz) Logic Size Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® V E 118 1022 (LE) 0.268 0.201
Intel® Cyclone® V 154 423 (ALM)
Intel® Arria® V 175 414 (ALM)
Intel® Arria® V GZ 289 372 (ALM)
Intel® Stratix® V 332 617 (ALM)
Intel® Cyclone® 10 LP 137 1025 (LE)
Intel® Arria® 10 325 355 (ALM)
Intel® MAX® 10 137 1022 (LE)
Table 5.  Benchmark Parameters for Intel® Quartus® Prime Standard Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/c processor core (without debug module and the internal timer 'timer_sw_agent' interface unconnected)
  • 128 KB on-chip memory for the instruction and data bus.
  • JTAG UART Intel® FPGA IP.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32i -mabi=ilp32

Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. The compiler settings are:

  • Superior Performance with Maximum Placement Effort in Intel® Quartus® Prime Pro Edition software.
  • High Performance Effort in Intel® Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design can change the performance and LE usage. All results are generated from design built with Platform Designer.