AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

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ID 683608
Date 5/24/2019
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

1.7.3. Running the Hardware Reference Design

Follow the steps below to run dynamic calibration and start the data transfer for the hardware reference design.

Remove all other connected devices in the programming device list during JTAG connection setup in your operating system.

  1. Open two Nios® II Command Shell prompts on your host machine:
    1. For Windows operating system:
      1. In the Intel® Quartus® Prime software installation directory in your host machine and double click on Nios® II Command Shell.bat to launch the command prompt window (command prompt A).
    2. For Linux operating system:
      1. Go to <Quartus software installation directory> \linux64\nios2ed directory and run nios2_command_shell.sh to launch the command prompt window (command prompt A).
    3. Repeat this step to launch the second command shell (command prompt B).
    Command prompt A is to display the dynamic calibration result. Command prompt B is used to run Nios® II commands.
  2. In command prompt A, use the following command to run the Nios® II terminal application for result printouts.
    nios2-terminal
  3. In command prompt B, go to the project top directory.
    cd <project directory>
  4. In command prompt B, download the executable (<project_name>.elf) file into the FPGA and start the dynamic calibration process with the following command:
    nios2-download -r -g software/<project_name>/<project_name>.elf

    or

    nios2-download -r -g software/phylite_top/a10_devkit.elf
    You may observe the passing dynamic calibration result displayed in command prompt A.
  5. When the Nios® II instruction memory is cleaned and calibration is done, run the following command in command prompt B to reset the system, start the random data transfer and capture internal signals.
    quartus_stp -t issp.tcl top.qpf 1 1
    Note: Sent and received data are displayed in command prompt B after running the command.
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