AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

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ID 683608
Date 5/24/2019
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Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

1.4.1. Register Address Map

Figure 4.  Intel® Arria® 10 Register Address Map
Notes to Figure 4:
  1. Pin[4:0]—Physical location of the pin in a lane. Refer to Appendix C: Decoding Parameter Table for more information.
  2. lane_addr[7:0]—Address of a given lane in an interface. The fitter sets this address value. Refer to Appendix C: Decoding Parameter Table for more information.
  3. Once the lane and pin addresses of the target PHY Lite for Parallel Interfaces interface is captured, the target pin can get reconfigured by Read/Write through calibration offset address, for example, cal_add = 3’b011.
  4. ID[3:0]—Interface ID parameter. This parameter distinguishes between different IP instances in an I/O column.
  5. For the physical addresses of lgc_sel and pin_off, refer to the Address Register for Pin Input Delay Feature table in the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP and PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX IP Cores Address Registers section of the PHY Lite for Parallel Interfaces Intel® FPGA IP Core User Guide.
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