AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

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ID 683608
Date 5/24/2019
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

1.10. Appendix B: Retrieving Lane and Pin Information

Information about each IP instance is stored in the I/O SSM named as parameter table.
You can access the parameter table via Avalon® interface at the base address offset 0xE000. The global parameter table lists all interfaces in the I/O column. Once the lane and pin addresses of the target PHY Lite for Parallel Interfaces interface is captured, the target pin can get reconfigured by Read/Write through calibration address offset of 0x80000. The base address offset, parameter table size offset, and interface offset are fixed, as defined in an algorithm shown in the following figure:
Figure 26. Flow Chart of Reading Parameter Table

The code block below is written in Nios® II processor to read out the parameter table as shown in Figure 27. 

#define BASE_ADDR           0xE000
#define PT_SIZE_PTR         0x0000014
#define ADDR_OFFSET         0x0000018
void Read_Param_table()
{
  int delay = -1;
  int addr_offset = -1;
  unsigned int size = 0;
  unsigned int value = 0;
  int i;

addr_offset = IORD32(BASE_ADDR+ADDR_OFFSET);
printf("Reading Addr Offset from Param Table: %08x\n\n",addr_offset);
size = IORD32(BASE_ADDR+PT_SIZE_PTR);
printf("Param Table size is %08x:\n", size);
printf("\nParam Table:\n");
for (addr=0x0; addr < size+1; addr += 4) {
value =  IORD32(BASE_ADDR+addr);
printf("%d\t%03x\t0x%08x\n",addr,value);
   }
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