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1.1. Features
1.2. Hardware and Software Requirements
1.3. Design System Architecture Overview
1.4. Dynamic Reconfiguration Overview
1.5. PHY Lite Per-Bit Overview
1.6. Compiling the Reference Design
1.7. Hardware Testing
1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1.9. Appendix A: HiLo Loopback Card Pin Connections
1.10. Appendix B: Retrieving Lane and Pin Information
1.11. Appendix C: Decoding Parameter Table
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1.7.4.1. Dynamic Calibration Result
The figures below show the per-bit calibration result log on command prompt A.
Figure 20. Calibration Result Log (Part 1 of 4)
Figure 21. Calibration Result Log (Part 2 of 4)
Figure 22. Calibration Result Log (Part 3 of 4)
Figure 23. Calibration Result Log (Part 4 of 4)