Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

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ID 683600
Date 6/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Intel Stratix 10 LL 40GbE IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device 12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
1. Datasheet x
1.1. Intel Stratix 10 LL 40GbE IP Core Supported Features 1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Intel Stratix 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Intel Stratix 10 LL 40GbE IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Intel Stratix 10 LL 40GbE Core
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Intel Stratix 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Intel Stratix 10 LL 40GbE Core Functional Description x
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath 4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Intel® Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core

6.3. Transceivers Signals

The transceivers require a separately instantiated advanced transmit (ATX) PLL to generate the high speed serial clock. For Intel Stratix 10 LL 40GbE IP core, you can use the same ATX PLL for all four transceivers. In many cases, the same ATX PLL can serve as input to additional transceivers that have similar input clocking requirements. In comparison to the fractional PLL (fPLL) and clock multiplier unit PLL, the ATX PLL has the best jitter performance and supports the highest frequency operation.
Table 15.   Transceiver Signals

Signal

Direction

Description

tx_serial[3:0] Output TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[3:0] Input RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 644.53125 MHz .
tx_serial_clk Input High speed serial clock driven by the ATX PLL. The frequency of this clock is 5.15625 GHz.

The IP core fans out the clock to target each of the four transceiver PHY links. You must drive this clock from a single TX transceiver PLL that you configure separately from the Intel Stratix 10 LL 40GbE IP core.

tx_pll_locked Input Lock signal from ATX PLL. Indicates the ATX PLL is locked.
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