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1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
Date | Intel® Quartus® Prime Version | IP version | Changes |
---|---|---|---|
2023.06.20 | 21.3 | 19.1.0 | Removed 0x340 register from Table: PHY Registers. |
2021.10.12 | 21.3 | 19.1.0 | Changed the device support level for the Intel® Stratix® 10 devices to Final. |
2021.03.08 | 20.3 | 19.1.0 | Removed the .sip file type from section: Generated File Structure. |
2020.10.05 | 20.3 | 19.1.0 |
|
2020.06.22 | 20.2 | 19.1.0 |
|
2019.12.13 | 19.3 | 19.1.0 |
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2019.09.30 | 19.3 | 19.1.0 |
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Date | Version | Changes |
---|---|---|
2017.05.08 | Quartus Prime Pro 17.1 Stratix 10 ES Editions |
|
2016.09.09 | Quartus Prime Pro-Stratix 10 Edition Beta | Initial release. |