Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core User Guide

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ID 683600
Date 6/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Intel Stratix 10 LL 40GbE IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives 11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device 12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
1. Datasheet x
1.1. Intel Stratix 10 LL 40GbE IP Core Supported Features 1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Intel Stratix 10 LL 40GbE Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Intel Stratix 10 LL 40GbE IP Core Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Intel Stratix 10 LL 40GbE IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Clock Requirements for 40GBASE-KR4/CR4 Variations 3.5.4. Adding the External TX MAC PLL 3.5.5. Placement Settings for the Intel Stratix 10 LL 40GbE Core
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Intel Stratix 10 LL 40GbE Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Intel Stratix 10 LL 40GbE Core Functional Description x
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath 4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Intel® Stratix® 10 Low Latency 40GBASE-KR4 IP Core Variations
4.1.1. Intel Stratix 10 LL 40GbE Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. Intel® Stratix® 10 LL 40GBASE-KR4/CR4 Registers 7.2. PHY Registers 7.3. TX MAC Registers 7.4. RX MAC Registers 7.5. Statistics Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core

4.1.2.2. IP Core Strict SFD Checking

The Intel Stratix 10 LL 40GbE core RX MAC checks all incoming packets for a correct Start byte (0xFB). If you turn on Enable Strict SFD check in the Intel Stratix 10 LL 40GbE parameter editor, you enable the RX MAC to check the incoming preamble and SFD for the following values:

  • SFD = 0xD5
  • Preamble = 0x555555555555

The RX MAC checks one or both of these values depending on the values in bits [4:3] of the RXMAC_CONTROL register at offset 0x50A.

Table 11.  Strict SFD Checking Configuration
Enable Strict SFD check 0x50A[4]: Preamble Check 0x50A[3]: SFD Check Fields Checked Behavior if Check Fails
Off Don't Care Don't Care Start byte IP core does not recognize a malformed Start byte as a Start byte
On 0 0 Start byte
0 1 Start byte and SFD IP Core drops the packet
1 0 Start byte and preamble
1 1 Start byte and preamble and SFD
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