Visible to Intel only — GUID: ewo1452727996519
Ixiasoft
1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
Visible to Intel only — GUID: ewo1452727996519
Ixiasoft
4.1.2. Intel Stratix 10 LL 40GbE Core RX MAC Datapath
The RX MAC receives Ethernet frames and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes. The RX MAC processes all incoming valid frames.
Figure 7. Flow of Client Frame With Preamble Pass-Through Turned On This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).
Figure 8. Flow of Client Frame With Preamble Pass-Through Turned Off This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).