Intel® Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.5.6. SDI Video Input/Output Ports

The Intel® Arria® 10 GX FPGA development board includes a SDI video port, which consists of a M23428G-33 cable driver and a M23544G-14 cable equalizer. The PHY devices from Macom interface to single-ended SMB connectors.

The cable driver supports operation from 125 Mbps to 11.88 Gbps. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.
Table 23.  SDI Video Output Standards for the SD and HD Input

SD_HD Input

Supported Output Standards

Rise Time

0

SMPTE 424M, SMPTE 292M

Faster

1

SMPTE 259M

Slower

Table 24.  SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions

Board Reference

Schematic Signal Name

FPGA Pin Number

I/O Standard

14

SDI_AVDD

—

—

2

SDI_AVDD

—

—

7

SDI_AVDD

—

—

9

SDI_SD_HDN

AW34

1.8 V

5

SDI_TX_RSET

—

—

1

SDI_TXCAP_N

D43

High Speed Differential I/O

16

SDI_TXCAP_P

D44

High Speed Differential I/O

10

SDI_TXDRV_N

—

—

11

SDI_TXDRV_P

—

—

Table 25.  SDI Cable Equalizer LengthsThe cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0, 6.0, and 11.88 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Cable Type

Data Rate (Mbps)

Maximum Cable Length (m)

Belden 1694A

270

400

Belden 1694A

1485

140

Belden 1694A

2970

120

Table 26.  SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board Reference

Schematic Signal Name

FPGA Pin Number

I/O Standard

9

AGCN

—

—

8

AGXP

—

—

10

MF0_BYPASS

AW32

1.8 V

19

MF1_AUTO_SLEEP

AY32

1.8 V

21

MF2_MUTE

AY35

1.8 V

22

MF3_XSD

—

—

6

MODE_SEL

—

—

11

MUTEREF

—

—

4

SDI_EQIN_N1

—

—

3

SDI_EQIN_P1

—

—

14

SDO_N / SDI_RX_N

H39

High Speed Differential I/O

15

SDO_P / SDI_RX_P

H40

High Speed Differential I/O
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