Intel® Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.5.5. DisplayPort

The Intel® Arria® 10 GX FPGA development board includes a DisplayPort connector.

Table 22.  DisplayPort Schematic Signal Names and Functions

Board Reference

Schematic Signal Name

FPGA Pin Number

I/O Standard

Description

13

DP_3P3V_CONFIG1

AK31

1.8 V

—

14

DP_3P3V_CONFIG2

AK32

1.8 V

—

18

DP_3P3V_HOT_PLUG

AM30

1.8 V

Hot plug detect

17

DP_AUX_CN

AM35

LVDS

Auxiliary channel (negative)

15

DP_AUX_CP

AN34

LVDS

Auxiliary channel (positive)

3

DP_ML_LANE_CN0

AP43

High Speed Differential I/O

Lane 0 (negative)

6

DP_ML_LANE_CN1

AM43

High Speed Differential I/O

Lane 1 (negative)

9

DP_ML_LANE_CN2

AH43

High Speed Differential I/O

Lane 2 (negative)

12

DP_ML_LANE_CN3

AF43

High Speed Differential I/O

Lane 3 (negative)

1

DP_ML_LANE_CP0

AP44

High Speed Differential I/O

Lane 0 (positive)

4

DP_ML_LANE_CP1

AM44

High Speed Differential I/O

Lane 1 (positive)

7

DP_ML_LANE_CP2

AH44

High Speed Differential I/O

Lane 2 (positive)

10

DP_ML_LANE_CP3

AF44

High Speed Differential I/O

Lane 3 (positive)

19

DP_RTN

AL33

High Speed Differential I/O

 Return for power
Level Two Title