Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

2.2. Performance and Resource Utilization

This section lists the resource utilization and performance data for various Intel FPGA device families. The estimates are obtained by compiling the core using the Intel® Quartus® Prime software.

The table below shows the resource utilization and performance data for a Stratix®  II GX device (EP2SGX130GF1508I4).

Table 2.  Memory Utilization and Performance Data for Stratix® II GX Devices
Channels ALUTs Logic Registers Memory Blocks fMAX

(MHz)

M512 M4K M-RAM
4 559 382 0 0 1 > 125
12 1617 1028 0 0 6 > 125

The table below shows the resource utilization and performance data for a Stratix®  III device (EP3SL340F1760C3). The performance of the IP Core in Stratix® IV devices is similar to Stratix®  III devices.

Table 3.  Memory Utilization and Performance Data for Stratix® III Devices
Channels ALUTs Logic Registers Memory Blocks fMAX

(MHz)

M9K M144K MLAB
4 557 345 37 0 0 > 125
12 1741 1028 0 24 0 > 125

The table below shows the resource utilization and performance data for a Cyclone®  III device (EP3C120F780I7).

Table 4.  Memory Utilization and Performance Data for Cyclone® III Devices
Channels Total Logic Elements Total Registers Memory

M9K

fMAX

(MHz)

4 711 346 37 > 125
12 2284 1029 412 > 125