Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

49.4. Intel FPGA GMII to RGMII Converter Core Interface

Figure 159.  Intel FPGA GMII to RGMII Converter Core Top Level Interfaces
Note: For more information and a detailed list of the interfaces denoted on this figure, refer to the corresponding interface name in the following tables.
Table 465.  peri_clock

Interface Name: peri_clock

Description: Peripheral clock interface.

Signal Width Direction Description
clk 1 Input Peripheral clock source.
Table 466.  peri_reset

Interface Name: peri_reset

Description: Peripheral reset interface.

Signal Width Direction Description
rst_n 1 Input

Active low peripheral asynchronous reset source.

This signal is asynchronously asserted and synchronously de-asserted. The synchronous de-assertion must be provided external to this core.

Table 467.  pll_25m_clock

Interface Name: pll_25m_clock

Description: 25MHz clock from FPGA PLL output.

Signal Width Direction Description
pll_25m_clk 1 Input 25MHz input clock from FPGA PLL.
Table 468.  pll_2_5m_clock

Interface Name: pll_2_5m_clock

Description: 2.5MHz clock from FPGA PLL output.

Signal Width Direction Description
pll_2_5m_clk 1 Input 2.5MHz input clock from FPGA PLL.
Table 469.  hps_gmii

Interface Name: hps_gmii

Description: GMII/MII interface facing Intel FPGA HPS Emac Interface Splitter Core

Signal Width Direction Description
mac_tx_clk_o 1 Input GMII/MII transmit clock from HPS
mac_tx_clk_i 1 Output GMII/MII transmit clock to HPS
mac_rx_clk 1 Output GMII/MII receive clock to HPS
mac_rst_tx_n 1 Input GMII/MII transmit reset source from HPS. Active low reset
mac_rst_rx_n 1 Input GMII/MII receive reset source from HPS. Active low reset
mac_txd 8 Input GMII/MII transmit data from HPS
mac_txen 1 Input GMII/MII transmit enable from HPS
mac_txer 1 Input GMII/MII transmit error from HPS
mac_rxdv 1 Output GMII/MII receive data valid to HPS
mac_rxer 1 Output GMII/MII receive data error to HPS
mac_rxd 8 Output GMII/MII receive data to HPS
mac_col 1 Output GMII/MII collision detect to HPS
mac_crs 1 Output GMII/MII carrier sense to HPS
mac_speed 2 Input MAC speed indication from HPS
Table 470.  phy_rgmii

Interface Name: phy_rgmii

Description: RGMII interface facing PHY device.

Signal Width Direction Description
rgmii_tx_clk 1 Output RGMII transmit clock to PHY
rgmii_rx_clk 1 In RGMII receive clock from PHY
rgmii_txd 4 Output RGMII transmit data to PHY
rgmii_tx_ctl 1 Output RGMII transmit control to PHY
rgmii_rxd 4 Input RGMII receive data from PHY
rgmii_rx_ctl 1 Input RGMII receive control from PHY