Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

12.4.1. HAL System Library Support

The Intel-provided driver implements a HAL character-mode device driver that integrates into the HAL system library for Nios® II and Nios® V processors systems. HAL users should access the JTAG UART via the familiar HAL API and the ANSI C standard library, rather than accessing the JTAG UART registers. ioctl() requests are defined that allow HAL users to control the hardware-dependent aspects of the JTAG UART.

Note: If your program uses the Intel-provided HAL device driver to access the JTAG UART hardware, accessing the device registers directly will interfere with the correct behavior of the driver.

For Nios® II and Nios® V processors users, the HAL system library API provides complete access to the JTAG UART core's features. Nios® II and Nios® V processors programs treat the JTAG UART core as a character mode device, and send and receive data using the ANSI C standard library functions, such as getchar() and printf().

The "Printing Characters to a JTAG UART core as stdout" example below demonstrates the simplest possible usage, printing a message to stdout using printf(). In this example, the Platform Designer system contains a JTAG UART core, and the HAL system library is configured to use this JTAG UART device for stdout.

Table 102.  Example: Printing Characters to a JTAG UART Core as stdout

#include <stdio.h>

int main ()

{

printf("Hello world.\n");

return 0;

}

The Transmitting characters to a JTAG UART Core example demonstrates reading characters from and sending messages to a JTAG UART core using the C standard library. In this example, the Platform Designer system contains a JTAG UART core named jtag_uart that is not necessarily configured as the stdout device. In this case, the program treats the device like any other node in the HAL file system.

Table 103.  Example: Transmitting Characters to a JTAG UART Core

/* A simple program that recognizes the characters 't' and 'v' */

#include <stdio.h>

#include <string.h>

int main ()

{

char* msg = "Detected the character 't'.\n";

FILE* fp;

char prompt = 0;

fp = fopen ("/dev/jtag_uart", "r+"); //Open file for reading and writing

if (fp)

{

while (prompt != 'v')

{ // Loop until we receive a 'v'.

prompt = getc(fp); // Get a character from the JTAG UART.

if (prompt == 't')

{ // Print a message if character is 't'.

fwrite (msg, strlen (msg), 1, fp);

}

if (ferror(fp)) // Check if an error occurred with the file
 clearerr(fp); // If so, clear it.

}

fprintf(fp, "Closing the JTAG UART file handle.\n");

fclose (fp);

}

return 0;

}

In this example, the ferror(fp) is used to check if an error occurred on the JTAG UART connection, such as a disconnected JTAG connection. In this case, the driver detects that the JTAG connection is disconnected, reports an error (EIO), and discards data for subsequent transactions. If this error ever occurs, the C library latches the value until you explicitly clear it with the clearerr() function.

For complete details of the HAL system library, refer to the Nios II Software Developer's Handbook .

The Nios® II Embedded Design Suite (EDS) provides a number of software example designs that use the JTAG UART core.