Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.5.1.2. ioctl() Operations

The Lightweight UART driver supports the ioctl() function to allow HAL-based programs to request device-specific operations. The table below defines the operation requests that the Lightweight UART driver supports.
Table 518.  UART ioctl() Operations
Request Description
TIOCEXCL Locks the device for exclusive access. Further calls to open() for this device will fail until either this file descriptor is closed, or the lock is released using the TIOCNXCL ioctl request. For this request to succeed there can be no other existing file descriptors for this device. The parameter arg is ignored
TIOCNXCL Releases a previous exclusive access lock. The parameter arg is ignored.

Additional operation requests are also optionally available for the fast driver only, as shown in Optional UART ioctl() Operations for the Fast Driver Only Table. To enable these operations in your program, you must set the preprocessor option—DINTEL_LW_UART_USE_IOCTL

Table 519.   Optional UART ioctl() Operations for the Fast Driver Only
Request Description
TIOCMGET Returns the current configuration of the device by filling in the contents of the input termios structure. A pointer to this structure is supplied as the value of the parameter opt.
TIOCMSET Sets the configuration of the device according to the values contained in the input termios structure. A pointer to this structure is supplied as the value of the parameter arg.
Note: The termios structure is defined by the Newlib C standard library. You can find the definition in the file <Nios II EDS install path>/components/altera_hal/HAL/inc/sys/termios.h.